/***********************************************************************************************************************
* DISCLAIMER
* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products.
* No other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all
* applicable laws, including copyright laws.
* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIESREGARDING THIS SOFTWARE, WHETHER EXPRESS, IMPLIED
* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NON-INFRINGEMENT.  ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY
* LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE FOR ANY DIRECT,
* INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR
* ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability
* of this software. By using this software, you agree to the additional terms and conditions found by accessing the
* following link:
* http://www.renesas.com/disclaimer
*
* Copyright (C) 2012, 2016 Renesas Electronics Corporation. All rights reserved.
***********************************************************************************************************************/

/***********************************************************************************************************************
* File Name    : r_cg_PlatformLink.h
* Version      : CodeGenerator for RL78/F13 V2.02.05.01 [11 Nov 2016]
* Device(s)    : R5F10PPJ
* Tool-Chain   : CCRL
* Description  : This file implements device driver for Serial module.
* Creation Date: 2017/5/8
***********************************************************************************************************************/

#ifndef CAN_H
#define CAN_H

#include "r_cg_macrodriver.h"

/***********************************************************************************************************************
Macro definitions (Register bit)
***********************************************************************************************************************/
/*
    CAN Global Configuration Register L
*/
/* Section of timestamp clock source select (TSSS) (GCFGL12) */
#define _0000_CAN_GCFGL_TSSS_0                   (0x0000U) /* fCLK/2 */
#define _1000_CAN_GCFGL_TSSS_1                   (0x1000U) /* CAN0 bit time clock */
/* Section of timestamp clock source devision (TSP) (GCFGL11 - GCFGL08) */
#define _0000_CAN_GCFGL_TSP_0                    (0x0000U) /* not divided */
#define _0100_CAN_GCFGL_TSP_1                    (0x0100U) /* divided by 2^1 */
#define _0200_CAN_GCFGL_TSP_2                    (0x0200U) /* divided by 2^2 */
#define _0300_CAN_GCFGL_TSP_3                    (0x0300U) /* divided by 2^3 */
#define _0400_CAN_GCFGL_TSP_4                    (0x0400U) /* divided by 2^4 */
#define _0500_CAN_GCFGL_TSP_5                    (0x0500U) /* divided by 2^5 */
#define _0600_CAN_GCFGL_TSP_6                    (0x0600U) /* divided by 2^6 */
#define _0700_CAN_GCFGL_TSP_7                    (0x0700U) /* divided by 2^7 */
#define _0800_CAN_GCFGL_TSP_8                    (0x0800U) /* divided by 2^8 */
#define _0900_CAN_GCFGL_TSP_9                    (0x0900U) /* divided by 2^9 */
#define _0A00_CAN_GCFGL_TSP_10                   (0x0A00U) /* divided by 2^10 */
#define _0B00_CAN_GCFGL_TSP_11                   (0x0B00U) /* divided by 2^11 */
#define _0C00_CAN_GCFGL_TSP_12                   (0x0C00U) /* divided by 2^12 */
#define _0D00_CAN_GCFGL_TSP_13                   (0x0D00U) /* divided by 2^13 */
#define _0E00_CAN_GCFGL_TSP_14                   (0x0E00U) /* divided by 2^14 */
#define _0F00_CAN_GCFGL_TSP_15                   (0x0F00U) /* divided by 2^15 */
/* Section of can clock source select (DCS) (GCFGL04) */
#define _0000_CAN_GCFGL_DCS_0                    (0x0000U) /* fCLK/2 */
#define _0010_CAN_GCFGL_DCS_1                    (0x0010U) /* fX */
/* Section of mirror function enable (MME) (GCFGL03) */
#define _0000_CAN_GCFGL_MME_0                    (0x0000U) /* disabled */
#define _0008_CAN_GCFGL_MME_1                    (0x0008U) /* enabled */
/* Section of DLC replacement enable (DRE) (GCFGL02) */
#define _0000_CAN_GCFGL_DRE_0                    (0x0000U) /* disabled */
#define _0004_CAN_GCFGL_DRE_1                    (0x0004U) /* enabled */
/* Section of DLC check enable (DCE) (GCFGL01) */
#define _0000_CAN_GCFGL_DCE_0                    (0x0000U) /* disabled */
#define _0002_CAN_GCFGL_DCE_1                    (0x0002U) /* enabled */
/* Section of transmit priority select (TPRI) (GCFGL00) */
#define _0000_CAN_GCFGL_TPRI_0                   (0x0000U) /* ID priority */
#define _0001_CAN_GCFGL_TPRI_1                   (0x0001U) /* transmit buffer number priority */

/*
    CAN Global Status Register
*/
/* Section of CAN RAM initialization status flag (GRAMINIT) (GSTS03) */
#define _08_CAN_GSTS_GRAMINIT_1                  (0x08U) /* CAN RAM initialization is ongoing */
/* Section of global stop status flag (GSLPSTS) (GSTS02) */
#define _04_CAN_GSTS_GSLPSTS_1                   (0x04U) /* in global stop mode */
/* Section of global test status flag (GHLTSTS) (GSTS01) */
#define _02_CAN_GSTS_GHLTSTS_1                   (0x02U) /* in global test mode */
/* Section of global reset status flag (GRSTSTS) (GSTS02) */
#define _01_CAN_GSTS_GRSTSTS_1                   (0x01U) /* in global reset mode */

/*
    CAN Global Control Register
*/
/* Section of transmit history buffer overflow interrupt enable (THLEIE) (GCTRL10) */
#define _0000_CAN_GCTRL_THLEIE_0                 (0x0000U) /* disabled */
#define _0400_CAN_GCTRL_THLEIE_1                 (0x0400U) /* enabled */
/* Section of FIFO message lost interrupt enable (MEIE) (GCTRL09) */
#define _0000_CAN_GCTRL_MEIE_0                   (0x0000U) /* disabled */
#define _0200_CAN_GCTRL_MEIE_1                   (0x0200U) /* enabled */
/* Section of DLC error interrupt enable (DEIE) (GCTRL08) */
#define _0000_CAN_GCTRL_DEIE_0                   (0x0000U) /* disabled */
#define _0100_CAN_GCTRL_DEIE_1                   (0x0100U) /* enabled */
/* Section of global stop mode (GSLPR) (GCTRL02) */
#define _0000_CAN_GCTRL_GSLPR_0                  (0x0000U) /* other than global stop mode */
#define _0004_CAN_GCTRL_GSLPR_1                  (0x0004U) /* global stop mode */
/* Section of global mode select (GMDC) (GCTRL01 - GCTRL00) */
#define _0000_CAN_GCTRL_GMDC_0                   (0x0000U) /* global operating mode */
#define _0001_CAN_GCTRL_GMDC_1                   (0x0001U) /* global reset mode */
#define _0002_CAN_GCTRL_GMDC_2                   (0x0002U) /* global test mode */

/*
    CAN0 Control Register L
*/
/* Section of Arbitration Lost Interrupt Enable (ALIE) (C0CTRL15) */
#define _0000_CAN_C0CTRL_ALIE_0                  (0x0000U) /* disabled */
#define _8000_CAN_C0CTRL_ALIE_1                  (0x8000U) /* enabled */
/* Section of Bus Lock Interrupt Enable (BLIE) (C0CTRL14) */
#define _0000_CAN_C0CTRL_BLIE_0                  (0x0000U) /* disabled */
#define _4000_CAN_C0CTRL_BLIE_1                  (0x4000U) /* enabled */
/* Section of Overload Frame Transmit Interrupt Enable (OLIE) (C0CTRL13) */
#define _0000_CAN_C0CTRL_OLIE_0                  (0x0000U) /* disabled */
#define _2000_CAN_C0CTRL_OLIE_1                  (0x2000U) /* enabled */
/* Section of Bus Off Recovery Interrupt Enable (BORIE) (C0CTRL12) */
#define _0000_CAN_C0CTRL_BORIE_0                 (0x0000U) /* disabled */
#define _1000_CAN_C0CTRL_BORIE_1                 (0x1000U) /* enabled */
/* Section of Bus Off Entry Interrupt Enable (BOEIE) (C0CTRL11) */
#define _0000_CAN_C0CTRL_BOEIE_0                 (0x0000U) /* disabled */
#define _0800_CAN_C0CTRL_BOEIE_1                 (0x0800U) /* enabled */
/* Section of Error Passive Interrupt Enable (EPIE) (C0CTRL10) */
#define _0000_CAN_C0CTRL_EPIE_0                  (0x0000U) /* disabled */
#define _0400_CAN_C0CTRL_EPIE_1                  (0x0400U) /* enabled */
/* Section of Error Warning Interrupt Enable (EWIE) (C0CTRL9) */
#define _0000_CAN_C0CTRL_EWIE_0                  (0x0000U) /* disabled */
#define _0200_CAN_C0CTRL_EWIE_1                  (0x0200U) /* enabled */
/* Section of Protocol Error Interrupt Enable (BEIE) (C0CTRL08) */
#define _0000_CAN_C0CTRL_BEIE_0                  (0x0000U) /* disabled */
#define _0100_CAN_C0CTRL_BEIE_1                  (0x0100U) /* enabled */
/* Section of Channel Stop Mode (CSLPR) (C0CTRL02) */
#define _0000_CAN_C0CTRL_CSLPR_0                 (0x0000U) /* other than channel stop mode */
#define _0004_CAN_C0CTRL_CSLPR_1                 (0x0004U) /* channel stop mode */
/* Section of Mode Select (CHMDC) (C0CTRL01 - C0CTRL00) */
#define _0000_CAN_C0CTRL_CHMDC_0                 (0x0000U) /* communication mode */
#define _0001_CAN_C0CTRL_CHMDC_1                 (0x0001U) /* reset mode */
#define _0002_CAN_C0CTRL_CHMDC_2                 (0x0002U) /* halt mode */

/*
    CAN0 Status Register L
*/
/* Section of Communication Status Flag (COMSTS) (C0STSL07) */
#define _0080_CAN_C0STSL_COMSTS_1                (0x0080U) /* Communication is ready */
/* Section of Receive Status Flag (RECSTS) (C0STSL06) */
#define _0040_CAN_C0STSL_RECSTS_1                (0x0040U) /* In reception */
/* Section of Transmit Status Flag (TRMSTS) (C0STSL05) */
#define _0020_CAN_C0STSL_TRMSTS_1                (0x0020U) /* In transmission or bus off state */
/* Section of Bus Off Status Flag (BOSTS) (C0STSL04) */
#define _0010_CAN_C0STSL_BOSTS_1                 (0x0010U) /* In bus off state */
/* Section of Error Passive Status Flag (EPSTS) (C0STSL03) */
#define _0008_CAN_C0STSL_EPSTS_1                 (0x0008U) /* In error passive state */
/* Section of Channel Stop Status Flag flag (CSLPSTS) (C0STSL02) */
#define _0004_CAN_C0STSL_CSLPSTS_1               (0x0004U) /* In channel stop mode */
/* Section of Channel Halt Status Flag (CHLTSTS) (C0STSL01) */
#define _0002_CAN_C0STSL_CHLTSTS_1               (0x0002U) /* In channel halt mode */
/* Section of Channel Reset Status Flag (CRSTSTS) (C0STSL00) */
#define _0001_CAN_C0STSL_CRSTSTS_1               (0x0001U) /* In channel reset mode */

/*
    CAN Global RAM Window Control Register
*/
/* Section of RAM Window Select (RPAGE) (GRWCR00) */
#define _0000_CAN_GRWCR_RPAGE_0                  (0x0000U) /* select window 0 */
#define _0001_CAN_GRWCR_RPAGE_1                  (0x0001U) /* select window 1 */

/*
    CAN0 Bit Configuration Register L
*/
/* Section of Prescaler Division Ratio Set (BRP) (C0CFGL09 - C0CFGL00) */
#define _0003_CAN_C0CFGL_BRP_3                   (0x0003U) /* divided fCAN by 4 */

/*
    CAN0 Bit Configuration Register H
*/
/* Section of Resynchronization Jump Width Control (SJW) (C0CFGH09 - C0CFGH08) */
#define _0000_CAN_C0CFGH_SJW_0                   (0x0000U) /* 1 Tq */
/* Section of Time Segment 2 Control (TSEG2) (C0CFGH06 - C0CFGH04) */
#define _0030_CAN_C0CFGH_TSEG2_3                 (0x0030U) /* 4 Tq */
/* Section of Time Segment 1 Control (TSEG1) (C0CFGH03 - C0CFGH00) */
#define _000A_CAN_C0CFGH_TSEG1_10                (0x000AU) /* 11 Tq */

/*
    CAN0 Bit Configuration Register L
*/
/* Section of Prescaler Division Ratio Set (BRP) (C0CFGL09 - C0CFGL00) */
#define _0003_CAN_C0CFGL_BRP_3                   (0x0003U) /* divided fCAN by 4 */

/*
    CAN Receive Rule Entry Register L
*/
#define _CAN_GAFLML_COMPARE_ALL                 (0xFFFFU) /* campare all */
/*
    CAN Receive Rule Entry Register H
*/
#define _CAN_GAFLMH_COMPARE_ALL                 (0xFFFFU) /* campare all */

/*
    CAN Receive Rule Entry Register L
*/
#define _CAN_GAFLML_COMPARE_ALL                 (0xFFFFU) /* campare all */
/*
    CAN Receive Rule Entry Register H
*/
#define _CAN_GAFLMH_COMPARE_ALL                 (0xFFFFU) /* campare all */

/*
    CAN Receive Rule Entry Register 0CL
*/
/* Section of Receive Buffer Enable (GAFLRMV) (GAFLPL15) */
#define _0000_CAN_GAFLPL_GAFLRMV_0               (0x0000U) /* No receive buffer is used */
#define _8000_CAN_GAFLPL_GAFLRMV_1               (0x8000U) /* A receive buffer is used */
/* Section of Receive Buffer Number Select (GAFLRMDP) (GAFLPL14 - GAFLPL08) */
#define _0000_CAN_GAFLPL_GAFLRMDP_0              (0x0000U) /* Set the receive buffer 0 to store receive */
/* Section of CAN0 Transmit/Receive FIFO Buffer Select 0 (GAFLFDP4) (GAFLPL04) */
#define _0000_CAN_GAFLPL_GAFLFDP4_0              (0x0000U) /* Not select a CAN0 transmit/receive FIFO buffer 0 */
#define _0010_CAN_GAFLPL_GAFLFDP4_1              (0x0010U) /* Select a CAN0 transmit/receive FIFO buffer 0 */
/* Section of Receive FIFO Buffer Select 1 (GAFLFDP1) (GAFLPL01) */
#define _0000_CAN_GAFLPL_GAFLFDP1_0              (0x0000U) /* Not select a receive FIFO buffer 1 */
#define _0002_CAN_GAFLPL_GAFLFDP1_1              (0x0002U) /* Select a receive FIFO buffer 1 */
/* Section of Receive FIFO Buffer Select 0 (GAFLFDP0) (GAFLPL00) */
#define _0000_CAN_GAFLPL_GAFLFDP0_0              (0x0000U) /* Not select a receive FIFO buffer 0 */
#define _0001_CAN_GAFLPL_GAFLFDP0_1              (0x0001U) /* Select a receive FIFO buffer 0 */

/*
    CAN Receive Rule Entry Register H
*/
/* Section of Receive Rule DLC (GAFLDLC) (GAFLPH15 - GAFLPH12) */
#define _0000_CAN_GAFLPH_GAFLDLC_0               (0x0000U) /* DLC check is disabled */
#define _1000_CAN_GAFLPH_GAFLDLC_1               (0x1000U) /* 1 data byte */
#define _2000_CAN_GAFLPH_GAFLDLC_2               (0x2000U) /* 2 data byte */
#define _3000_CAN_GAFLPH_GAFLDLC_3               (0x3000U) /* 3 data byte */
#define _4000_CAN_GAFLPH_GAFLDLC_4               (0x4000U) /* 4 data byte */
#define _5000_CAN_GAFLPH_GAFLDLC_5               (0x5000U) /* 5 data byte */
#define _6000_CAN_GAFLPH_GAFLDLC_6               (0x6000U) /* 6 data byte */
#define _7000_CAN_GAFLPH_GAFLDLC_7               (0x7000U) /* 7 data byte */
#define _8000_CAN_GAFLPH_GAFLDLC_8               (0x8000U) /* 8 data byte */

/*
    CAN Receive Rule Entry Register L
*/
/* Section of Receive Buffer Enable (GAFLRMV) (GAFLPL15) */
#define _0000_CAN_GAFLPL_GAFLRMV_0               (0x0000U) /* No receive buffer is used */
#define _8000_CAN_GAFLPL_GAFLRMV_1               (0x8000U) /* A receive buffer is used */
/* Section of Receive Buffer Number Select (GAFLRMDP) (GAFLPL114 - GAFLPL08) */
#define _0100_CAN_GAFLPL_GAFLRMDP_1              (0x0100U) /* Set the receive buffer 1 to store receive */
/* Section of CAN0 Transmit/Receive FIFO Buffer Select 0 (GAFLFDP4) (GAFLPL04) */
#define _0000_CAN_GAFLPL_GAFLFDP4_0              (0x0000U) /* Not select a CAN0 transmit/receive FIFO buffer 0 */
#define _0010_CAN_GAFLPL_GAFLFDP4_1              (0x0010U) /* Select a CAN0 transmit/receive FIFO buffer 0 */
/* Section of Receive FIFO Buffer Select 1 (GAFLFDP1) (GAFLPL01) */
#define _0000_CAN_GAFLPL_GAFLFDP1_0              (0x0000U) /* Not select a receive FIFO buffer 1 */
#define _0002_CAN_GAFLPL_GAFLFDP1_1              (0x0002U) /* Select a receive FIFO buffer 1 */
/* Section of Receive FIFO Buffer Select 0 (GAFLFDP0) (GAFLPL00) */
#define _0000_CAN_GAFLPL_GAFLFDP0_0              (0x0000U) /* Not select a receive FIFO buffer 0 */
#define _0001_CAN_GAFLPL_GAFLFDP0_1              (0x0001U) /* Select a receive FIFO buffer 0 */

/*
    CAN Receive Rule Entry Register H
*/
/* Section of Receive Rule DLC (GAFLDLC) (GAFLPH15 - GAFLPH12) */
#define _0000_CAN_GAFLPH_GAFLDLC_0               (0x0000U) /* DLC check is disabled */
#define _1000_CAN_GAFLPH_GAFLDLC_1               (0x1000U) /* 1 data byte */
#define _2000_CAN_GAFLPH_GAFLDLC_2               (0x2000U) /* 2 data byte */
#define _3000_CAN_GAFLPH_GAFLDLC_3               (0x3000U) /* 3 data byte */
#define _4000_CAN_GAFLPH_GAFLDLC_4               (0x4000U) /* 4 data byte */
#define _5000_CAN_GAFLPH_GAFLDLC_5               (0x5000U) /* 5 data byte */
#define _6000_CAN_GAFLPH_GAFLDLC_6               (0x6000U) /* 6 data byte */
#define _7000_CAN_GAFLPH_GAFLDLC_7               (0x7000U) /* 7 data byte */
#define _8000_CAN_GAFLPH_GAFLDLC_8               (0x8000U) /* 8 data byte */

/*
    CAN0 Transmit Buffer Status Register
*/
/* Section of Transmit Buffer Transmit Abort Request Status Flag (TMTARM) (TMSTS04) */
#define _0010_CAN_TMSTS_TMTARM_1                (0x0010U) /* A transmit abort request is present */
/* Section of Transmit Buffer Transmit Request Status Flag (TMTRM) (TMSTS03) */
#define _0008_CAN_TMSTS_TMTRM_1                 (0x0008U) /* A transmit request is present */
/* Section of Transmit Buffer Transmit Result Flag  (TMTRF) (TMSTS02 - TMSTS01) */
#define _0000_CAN_TMSTS_TMTRF_0                 (0x0000U) /* Transmission is in progress or no transmit request is present */
#define _0002_CAN_TMSTS_TMTRF_1                 (0x0002U) /* Transmit abort has been completed */
#define _0004_CAN_TMSTS_TMTRF_2                 (0x0004U) /* Transmission has been completed (without transmit abort request) */
#define _0006_CAN_TMSTS_TMTRF_3                 (0x0006U) /* Transmission has been completed (with transmit abort request) */
/* Section of Transmit Buffer Transmit Status Flag (TMTSTS) (TMSTS00) */
#define _0001_CAN_TMSTS_TMTSTS_1                (0x0001U) /* Transmission is in progress */

/*
    CAN0 Transmit Buffer Control Register
*/
/* Section of One-Shot Transmission Enable (TMOM) (TMC02) */
#define _00_CAN_TMC_TMOM_0               (0x00U) /* One-shot transmission is disabled */
#define _04_CAN_TMC_TMOM_1               (0x04U) /* One-shot transmission is enabled */
/* Section of CAN0 Transmit/Receive FIFO Buffer Select 0 (GAFLFDP4) (TMC01) */
#define _00_CAN_TMC_TMTAR_0              (0x00U) /* Transmit abort is not requested */
#define _02_CAN_TMC_TMTAR_1              (0x02U) /* Transmit abort is requested */
/* Section of Receive FIFO Buffer Select 1 (GAFLFDP1) (TMC00) */
#define _00_CAN_TMC_TMTR_0               (0x00U) /* Transmission is not requested */
#define _01_CAN_TMC_TMTR_1               (0x01U) /* Transmission is requested */


/***********************************************************************************************************************
Macro definitions
***********************************************************************************************************************/


/***********************************************************************************************************************
Typedef definitions
***********************************************************************************************************************/

/***********************************************************************************************************************
Global functions
***********************************************************************************************************************/
void R_CAN0_Create(void);
uint8_t R_CAN0_Is_Received(uint8_t buffer_num);
uint8_t R_CAN0_Read(uint8_t buffer_num, uint16_t * id_hi, uint16_t * id_lo, uint8_t * rx_buf);
uint8_t R_CAN0_Is_Transmitted(uint8_t buffer_num);
void R_CAN0_Send(uint16_t id_hi, uint16_t id_lo, uint8_t length, uint8_t * tx_buf);
void R_CAN0_Set_Rx_Buffer(uint8_t buffer_num, uint16_t id_hi, uint16_t id_lo, uint16_t mask_hi, uint16_t mask_lo);
void R_CAN0_Set_Baudrate(uint16_t baud_rate);

#endif
